The present invention relates to a power amplifier or controller for a DC motor, and more particularly to a device characterized by a near zero off-duty current drain.
DC motor control has previously been accomplished by use of semiconductor devices. FIGS. 1a-c are illustrative of one type of semiconductor power controller consisting of four switches SW1-4 to control a motor or load generally shown as M. In the off-state switches SW3 and SW4 are closed, thereby applying a short circuit clamp across the motor M. As it is known in the art dynamic braking is achieved by short-circuiting the motor terminals A and B in an armature controlled permanent magnet DC motor. Forward motion of the load or motor is accomplished by closing switches SW1 and SW4. In this condition current will flow from terminal A to terminal B. Alternatively, closing switches SW2 and SW3 causes a reversal of current flow from terminal B to terminal A, thereby reversing the direction of the load or motor. By utilizing the teachings of the circuit in FIGS. 1, a basic semiconductor power controller can be constructed. As illustrated in FIG. 2a, the controller 20 utilizes Metal-Oxide Silicone Field Effect Transistors (MOSFET) While FIG. 2a illustrates an N-type MOFSET, P-type MOSFETS can be used. If this were the case, the voltage polarity in the current directions described will be reversed FIG. 2c is illustrative of a complementary symmetry circuit using P-type MOSFETS.
MOSFETS typically include three active terminals, a gate (G) terminal, a drain (D) terminal, and a source (S). These three active terminals are illustrated with reference to transistor Q5 which corresponds to switch SW1. As is known in the art the MOSFET transistor Q5 further includes an additional terminal (B) corresponding to the active bulk or substrate of the transistor. With reference to FIGS. 1 and 2a, switches SW1-4, have been realized by four MOSFET transistors Q5, Q6, Q13 and Q14. The load such as motor (M) extends between terminals A and B which are defined as the junction between the source and drain terminals of the various respective pairs of transistors Q5-Q13 and Q6-Q14, respectively.
As can be seen in FIG. 2a, the drain terminals of transistors Q5 and Q6 are connected to a positive voltage potential (+V) while the source terminals of transistors Q13 and Q14 are connected to a negative source of potential (-V). If the present invention is used in a mobile environment, voltage source may be implemented by an automotive battery with +V equal to B+ and and -V equal to ground. The gate terminal of transistor Q13 is connected to receive a logic signal /FWD at terminal 24 and the gate terminal of transistor Q14 connected to receive another logic signal /REV at terminal 26. Logic signals /FWD and /REV are binary changing from +V to -V. Proper scientific notation would represent a complementary logic signal by a bar over the basic signal. This notation is used in the figures, however, in the written specification logical complementary signals are typed as /FWD, /REV, etc. The logic signals /FWD and /REV are connected to charge pump circuits 22a and b respectively. These charge pump circuits 22a and b are also controlled by a charge pump drive signal received at terminal C. The output of these charge pump circuits are connected to the gate terminal of transistors Q5 and Q6 respectively. It should be appreciated that to turn MOSFET devices such as those shown in FIG. 2a to an ON state requires an applied voltage potential at the gate terminal which is more positive than the respective source terminal. This function is achieved by the charge pump circuit which in simple terms generates an output signal substantially greater than the value of the positive voltage potential (+V). FIG. 2b illustrates a rudimentary charge pump circuit 22a connected to positive and negative voltage potentials. The charge pump circuit 22a comprises capacitor C1, diodes D1 and D2 and a switch generally designated as SWT. The charge pump circuit such as circuit 22a is controlled by a gate signal which as shown below can be either of the /FWD and /REV signals or related signals. The capacitance CG (shown in dotted line) between the gate terminal and the negative voltage potential (-V) represents the effective capacitive input between the gate and source terminals of the MOSFET devices such as Q5 or Q6. The switch SWT is a single pole double-throw switch which alternatively switches one side of capacitor C1 between the positive and negative voltage potentials (+V and -V). With switch SWT closed and connected to the negative voltage potential (-V), the capacitor C1 will charge through diode D1 such that its terminal nearest the switch SWT is negatively charged. The other terminal near the junction of the two diodes will, of course, be charged positively. When the switch SWT is moved in contact with the positive voltage potential (+V) the effective gate-to-source capacitance CG would be charged through diodes D1 and D3 to the level of the positive voltage potential (+V) and by the voltage stored on capacitor C1 through diode D3 such that the voltage across capacitor CG will be approximately equal to: V.sub.CG =2*V*C1/(C1+CG). During the next pumping cycle the voltage will again increase across capacitor CG and this process is continued until the voltage across the effective capacitance CG is approximately equal to twice the positive voltage potential. The above relationship can be approximated by: V.sub.CG =2*V*[1-a.sup.k ] where a=CG/(C1+CG) and k is the number of charge pumping cycles. Since a 1 as k increases a k.fwdarw. and V.sub.CG .fwdarw.2V. As is known in the art and appreciated as a practical matter, the gate-to-source capacitance of the devices Q5 or Q6 must be discharged as soon as the supply voltage to the load (M) is switched off, i.e., this will occur when transistors Q13 and Q14 are simultaneously switched on and occurs when /FWD=+V and /REV=+V. In addition, the other charge pumping such as 22b must not be activated on a non-driving side of the circuit shown in FIG. 2a, i.e., on the side of transistor Q6 in the case of a /FWD drive signal or on side Q5 in the case of a /REV drive signal. As an example, in the FWD (forward) mode, i.e., /FWD=-V transistors Q5 and Q14 are on, and charge pumping is achieved on the side of Q5. If the charge pumping was also achieved on the side of Q6, it would also be turned on. In that case the conducting transistors Q6 and Q14 would present a near short circuit between +V and -V lines. Briefly returning to FIG. 2a, the /FWD and /REV signals are shown which will cause the load or motor (M) to drive in a forward direction. The signals of course will be reversed to drive the motor in the opposite direction with /FWD=/REV=+V the motor is deactivated or stopped.
With reference to FIG. 2c, Transistors Q5 and Q6 are P-type MOFSETS which can be turned on by making their gates more negative than their sources. If control signal /FWD and /REV swing between -V and +V, then in the quiescent state both /FWD and /REV are at +V, causing transistors Q13 and Q14 to be fully turned on and Q5 and Q6 to be fully turned off. If /FWD is switched to -V while /REV is held at +V, transistors Q5 and Q14 are turned on, transistors Q6 and Q13 are turned off, thus causing the load current to flow from terminal A to B (positive, or forward drive). If, on the other hand, /REV is switched to -V while /FWD is held at +V, transistors Q6 and Q13 will be fully turned on and Q5 and Q14 will be fully turned off causing the current to flow from terminal B to A.
In spite of the fact that the complementary symmetry circuit of FIG. 2c is conceptually much simpler than FIG. 2a, it is subject to severe limitations. For instance, it is difficult to find P-type MOSFET devices which can conduct more than -20 amperes continuously. In addition, P-type MOSFET devices are much more expensive than the N-types.
If currents greater than 20 amperes must be handled or cost is an important factor, a configuration of the type shown in FIG. 2a is the only viable method.
An object of the present invention is to provide a semiconductor power controller for a motor whereby the standby current drain is essentially zero amperes. A further object of the present invention is to incorporate within such power amplifier a gated charge pump circuit. Accordingly, the present invention, in its simplest form comprises: a power controller for a load such as a DC motor comprising:
direction switch comprising a MOSFET transistor direction switch comprising a MOSFET transistor adapted to be connected between a positive voltage potential (+V) and one terminal of the load for causing the load to move, when activated, in a first direction. The power controller additionally includes first charge pump means associated with the first direction switch. The first charge pump means includes first means (Q1, D1, D3, C1) for generating a first voltage signal in a response to a first state of a first control signal, at the gate terminal of the first direction switch substantially larger, in an absolute sense, than the value of the positive voltage potential (+V), for driving such switch between conductive and nonconductive states and second means, operative when the first direction switch is in a nonconductive state, for discharging the gate-to-source capacitance, associated with the first direction switch. The controller in practice includes four MOSFET transistor switches arranged in an H-bridge the upper switches each having associated therewith a charge pump for controllably activating same in response to complementary sets of first and second control signals. Each charge pump includes means for discharging the gate-to source capacitance of these switches. The two charge pumps are driven by a common charge pump drive circuit which generates a substantially, square wave charge pump drive signal which oscillates between a given voltage range to charge corresponding capacitors to a level to place the upper switches in a conductive state.
Many other objects and purposes of the invention will be clear from the following detailed description of the drawings.